This circuit is designed to flip the polarity of its input, controlled via a signal between ±10 VDC. The input can have up to ±1000 VDC per conductor. When the control signal goes LOW, the first output pair is engaged and the input polarity is maintained. When the control signal goes HIGH (rising above 5 VDC), the second output pair is engaged and the input polarity is flipped at the output. The control signal can be generated by a CMOS compatible digital output.
Two pairs of reed relays map the input to output with opposing polarities. One pair of relays activates when the control signal is LOW (pair 1, polarity maintaining), and the other activates when it’s HIGH (pair 2, polarity switching). During switch-over, the circuit uses a delay circuit to "break before make", to avoid momentarily shorting the output terminals together. Components C17, C18, R8 and R9 are used to match the impedance and capacitance of any transmission lines connected at the outputs. Size C18 and C18 to match the transmission lines’ capacitance, and set R8 and R9 to their characteristic impedance. Components D3 and D4 are used to snub any residual transients due to impedance mismatch to ground.
The time constant of the RC filter determines the time it takes for the capacitor to discharge to 37% (1/e) of its peak voltage. As the logic gates are CMOS type, the threshold where a logic output of HIGH flips to LOW occurs at 40%, so the time constant essentially sets the switch delay. The delay must be longer than the switching time of the reed relays, which is around 1 ms. The suggested 3 kΩ resistor and 1 μF capacitor give a time constant of 3 ms.
The circuit requires a ±19 VDC power supply.